1. Technical Field of the Invention
The present invention relates to the field of integrated circuit, and more particularly to three-dimensional memory (3D-M).
2. Prior Arts
Three-dimensional memory (3D-M) is a semiconductor memory comprising a plurality of vertically stacked memory levels. It includes three-dimensional read-only memory (3D-ROM) and three-dimensional random-access memory (3D-RAM). The 3D-ROM can be further categorized into three-dimensional mask-programmed read-only memory (3D-MPROM) and three-dimensional electrically-programmable read-only memory (3D-EPROM). Based on programming mechanism, 3D-M may be categorized into memristor, resistive random-access memory (RRAM or ReRAM), phase-change memory, programmable metallization cell (PMC), and conductive-bridging random-access memory (CBRAM).
U.S. Pat. Nos. 5,835,396 and 6,717,222 disclose various 3D-Ms. As illustrated in FIG. 1, a 3D-M die 20 comprises a substrate level 0K and a plurality of vertically stacked memory levels 16A, 16B. The substrate level 0K comprises transistors 0t and interconnects 0i. Transistors 0t are formed in a semiconductor substrate 0, while interconnects 0i, including substrate metal layers 0M1, 0M2, are formed above the substrate 0 but below the lowest memory level 16A. Each of the memory levels (e.g. 16A) comprises a plurality of upper address lines (e.g. 2a), lower address lines (e.g. 1a) and memory cells (e.g. 5aa). The memory cells could use diodes, transistors or other devices. The memory levels (e.g. 16A) are coupled to the substrate 0 through contact vias (e.g. 1av). In this figure, the memory levels 16A, 16B form a plurality of 3D-M arrays 22, while the substrate level 0K comprises the peripheral circuits 28 for the 3D-M arrays 22. Generally speaking, the space 26 above the peripheral circuit 28 does not contain any memory cells. Since the 3D-M arrays 22 and their peripheral circuits 28 are integrated onto a same substrate 0, the 3D-M die 20 is referred to as an integrated 3D-M die.
FIG. 2 discloses more details on the memory-array region 22 and the peripheral-circuit region 28 in an integrated 3D-M die 20 (referring to Crowley et al. “512 Mb PROM with 8 layers of antifuse/diode cells”, 2003 International Solid-State Circuits Conference, FIG. 16.4.5). The memory-array region 22 comprises a plurality of 3D-M arrays (e.g. 22aa, 22ay) and their decoders (e.g. 24, 24G). These decoders include local decoders 24 and global decoders 24G. The local decoder 24 decodes address/data for a single 3D-M array, while the global decoder 24G decodes the external address/data to each individual 3D-M array. On the other hand, the peripheral-circuit region 28 comprises all peripheral-circuit components for the 3D-M. The peripheral-circuit components include charge-pump circuit 21, page register 23 and trim-bit circuit 25. Here, the charge-pump circuit 21 generates the programming voltage and/or read voltage for the 3D-M; the page register 23 temporarily stores the data from a 3D-M page; the trim-bit circuit 25 records the faulty blocks in the 3D-M. Because the peripheral-circuit region 28 comprises all peripheral-circuit components and occupies a large die area, the array-efficiency of the integrated 3D-M die 20 is generally less than 70%.
It is a prevailing belief that integration will always reduce the manufacturing cost of the integrated circuit. This is not true for the 3D-M. Because the 3D-M arrays use a complex back-end process while their peripheral circuits use a relatively simple back-end process, integrating the 3D-M arrays with their peripheral circuits will force the peripheral circuits to use the expensive manufacturing process for the 3D-M arrays. As a result, integration does not reduce the manufacturing cost of the 3D-M, but actually increases it. In addition, because the peripheral circuits is constrained by the 3D-M arrays in the number of the substrate metal layers, the peripheral circuits are difficult to design and occupy a large die area. Furthermore, because the 3D-M cells generally require high-temperature processing, the peripheral circuits need to use high-temperature interconnect materials, e.g. tungsten (W). These materials degrade the overall 3D-M performance.